Somayeh Timarchi: search on Z-Library

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1

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles

Mahdavi, Hossein, Timarchi, Somayeh

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2020

Language:

english

File:

PDF, 819 KB

english, 2020

2

[IEEE 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) - Tehran, Iran (2015.10.7-2015.10.8)] 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) - Maximally redundant high-radix Signed-Digit Residue Number System

Timarchi, Somayeh, Akbarzadeh, Negar, Hamidi, Amir Abbas

Year:

2015

Language:

english

File:

PDF, 507 KB

english, 2015

3

Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix

Shabani, Ahmad, Timarchi, Somayeh, Mahdavi, Hossein

Journal:

Microelectronics Journal

Year:

2019

Language:

english

File:

PDF, 5.41 MB

english, 2019

4

A novel low-power full-adder cell for low voltage

Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei

Journal:

Integration, the VLSI Journal

Year:

2009

Language:

english

File:

PDF, 762 KB

english, 2009

5

[IEEE 2010 IEEE International Conference on Computer Design (ICCD 2010) - Amsterdam, Netherlands (2010.10.3-2010.10.6)] 2010 IEEE International Conference on Computer Design - A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation

Timarchi, Somayeh, Fazlali, Mahmood, Cotofana, Sorin D.

Year:

2010

Language:

english

File:

PDF, 1.22 MB

english, 2010

6

[IEEE 2012 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS) - Shiraz, Fars, Iran (2012.05.2-2012.05.3)] The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012) - A novel high-speed low-power binary signed-digit adder

Timarchi, Somayeh, Ghayour, Parham, Shahbahrami, Asadollah

Year:

2012

Language:

english

File:

PDF, 122 KB

english, 2012

7

[IEEE 2007 IEEE International Symposium on Intelligent Signal Processing - Alcala de Henares, Spain (2007.10.3-2007.10.5)] 2007 IEEE International Symposium on Intelligent Signal Processing - Efficient Class of Redundant Residue Number System

Timarchi, Somayeh, Navi, Keivan

Year:

2007

Language:

english

File:

PDF, 3.82 MB

english, 2007

8

[IEEE 2009 IEEE Computer Society Annual Symposium on VLSI - Tampa, Florida, USA (2009.05.13-2009.05.15)] 2009 IEEE Computer Society Annual Symposium on VLSI - Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

Timarchi, Somayeh, Navi, Keivan, Kavehei, Omid

Year:

2009

Language:

english

File:

PDF, 324 KB

english, 2009

9

[IEEE 2010 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS) - Tehran, Iran (2010.09.23-2010.09.24)] 2010 15th CSI International Symposium on Computer Architecture and Digital Systems - An efficient power-area-delay modulo 2n−1 multiplier

Timarchi, Somayeh, Fazlali, Mahmood

Year:

2010

Language:

english

File:

PDF, 472 KB

english, 2010

10

Efficient Reverse Converter Designs for the New 4-Moduli Sets $\{2^{n} -1, 2^{n}, 2^{n} +1, 2^{2n + 1}-1\}$ and $\{2^{n} -1, 2^{n} +1, 2^{2n}, 2^{2n} +1\}$ Based on New CRTs

Molahosseini, Amir Sabbagh, Navi, Keivan, Dadkhah, Chitra, Kavehei, Omid, Timarchi, Somayeh

Journal:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Year:

2010

Language:

english

File:

PDF, 2.06 MB

english, 2010

11

[IEEE 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) - Istanbul, Turkey (2013.10.7-2013.10.9)] 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) - High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding

Timarchi, Somayeh, Saremi, Maryam, Fazlali, Mahmood, Gaydadjiev, Georgi

Year:

2013

Language:

english

File:

PDF, 231 KB

english, 2013

12

[IEEE 2013 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS) - Tehran, Iran (2013.10.30-2013.10.31)] The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013) - Efficient 1-out-of-3 Binary Signed-Digit multiplier for the moduli set {2n-1, 2n, 2n+1}

Saremi, Maryam, Timarchi, Somayeh

Year:

2013

Language:

english

File:

PDF, 227 KB

english, 2013

13

[IEEE 2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) - Opatija, Croatia (2014.5.26-2014.5.30)] 2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) - High-speed energy-efficient 5:2 compressor

Najafi, Ardalan, Timarchi, Somayeh, Najafi, Amir

Year:

2014

Language:

english

File:

PDF, 309 KB

english, 2014

14

[IEEE 2014 22nd Iranian Conference on Electrical Engineering (ICEE) - Tehran, Iran (2014.5.20-2014.5.22)] 2014 22nd Iranian Conference on Electrical Engineering (ICEE) - Radix-4 implementation of redundant interleaved modular multiplication on FPGA

Rahimzadeh, Loghman, Eshghi, Mohammad, Timarchi, Somayeh

Year:

2014

Language:

english

File:

PDF, 226 KB

english, 2014

15

Fast architecture for decimal digit multiplication

Fazlali, Mahmood, Valikhani, Hadi, Timarchi, Somayeh, Malazi, Hadi Tabatabaee

Journal:

Microprocessors and Microsystems

Year:

2015

Language:

english

File:

PDF, 1.02 MB

english, 2015

16

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Moghaddam, Majid, Timarchi, Somayeh, Moaiyeri, Mohammad Hossein, Eshghi, Mohammad

Journal:

Circuits, Systems, and Signal Processing

Year:

2016

Language:

english

File:

PDF, 3.10 MB

english, 2016

17

[IEEE 2015 9th Iranian Conference on Machine Vision and Image Processing (MVIP) - Tehran, Iran (2015.11.18-2015.11.19)] 2015 9th Iranian Conference on Machine Vision and Image Processing (MVIP) - Efficient multiply-add unit specified for DSPs utilizing low-power pipeline modulo 2n+1 multiplier

Akbarzadeh, Negar, Timarchi, Somayeh, Hamidi, Amir Abbas

Year:

2015

Language:

english

File:

PDF, 1.71 MB

english, 2015

18

Efficient modulo 2n +1 multiplier

Alaie, Masoud Abbasi, Timarchi, Somayeh

Journal:

International Journal of Computer Aided Engineering and Technology

Year:

2016

Language:

english

File:

PDF, 695 KB

english, 2016

19

A new algorithm for determining all possible symmetric hybrid redundant numbers

Timarchi, Somayeh, Navi, Keivan

Journal:

IEICE Electronics Express

Year:

2009

Language:

english

File:

PDF, 228 KB

english, 2009

20

[IEEE 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) - Monte Carlo, Monaco (2016.12.11-2016.12.14)] 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) - Ultra-low voltage standard cell libraries: Design strategies and a case study

Timarchi, Somayeh, Alioto, Massimo

Year:

2016

Language:

english

File:

PDF, 346 KB

english, 2016

21

Low-power DCT-based compressor for wireless capsule endoscopy

Shabani, Ahmad, Timarchi, Somayeh

Journal:

Signal Processing: Image Communication

Year:

2017

Language:

english

File:

PDF, 2.03 MB

english, 2017

22

[IEEE 2017 19th International Symposium on Computer Architecture and Digital Systems (CADS) - Kish Island, Iran (2017.12.21-2017.12.22)] 2017 19th International Symposium on Computer Architecture and Digital Systems (CADS) - Novel algorithm and architectures for high-speed low-power ConText-based steganography

Timarchi, Somayeh, Alaei, Masoud Abbasi, Koushkbaghi, Hossein

Year:

2017

File:

PDF, 940 KB

2017

23

Optimized Parity-Based Error Detection and Correction Methods for Residue Number System

Armand, Adib, Timarchi, Somayeh, Mahdavi, Hossein

Journal:

Journal of Circuits System and Computers

Year:

2018

Language:

english

File:

PDF, 668 KB

english, 2018

24

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Naseri, Hamed, Timarchi, Somayeh

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 4.31 MB

english, 2018

25

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier

Timarchi, Somayeh, Akbarzadeh, Negar

Journal:

Circuits, Systems, and Signal Processing

Year:

2018

Language:

english

File:

PDF, 3.34 MB

english, 2018

26

Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Mahdavi, Hossein, Timarchi, Somayeh

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2019

Language:

english

File:

PDF, 34 KB

english, 2019

27

Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Mahdavi, Hossein, Timarchi, Somayeh

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2019

File:

PDF, 34 KB

2019